1. Field of the Invention
The present invention relates to mask ROMs and the method of manufacturing thereof, and more particularly, to a mask ROM advantageous to larger memory capacity, and the method of manufacturing thereof.
2. Description of the Background Art
The memory ICs used today are typically classified according to its writing characteristic into a RWM (read write memory) that can read out and be written freely after manufacturing, and a ROM (read only memory) that cannot be written and is used exclusively for reading after manufacturing. ROMs are used for storing fixed information such as character patterns because the stored information is nonvolatile, i.e. does not disappear, and remains even after power supply is cut off. ROMs can further be classified into an EPROM (Erasable and Programmable ROM) that can have the stored information electrically modified and erased by ultraviolet light irradiation after manufacturing, and a mask ROM that can not have the stored information that is written during the manufacturing step modified after manufacturing. Mask ROMs are widely used for storing fixed data such as the character patterns of CRT displays and BASIC programs of personal computers.
The memory array portion of a mask ROM available in the market includes a MOS transistor arranged in a matrix. Such a MOS transistor is used as a memory cell. In forming a MOS transistor on a semiconductor substrate, three regions of source/drain and gate are required. The size of these three regions must be sufficient to realize the function as a MOS transistor, and thus cannot be minimized without restriction. Contrary to the request for minimization of semiconductor integrated circuit devices, there was a limit in reducing the area size of the entire memory array. This became a serious problem as the storage capacity of a mask ROM increased. The need of large storage capacity of a memory IC including a mask ROM is drastically growing these years. Therefore, a mask ROM satisfying the contradicting requirements of miniaturization of various semiconductor integrated circuit devices including a memory IC and of increase in the memory capacity of a memory IC are now being studied from both the standpoints of miniaturization of each memory cell and increase in the number of bits of information stored in each memory cell.
A mask ROM devised from the standpoint of miniaturization of each memory cell will first be explained.
According to such an improved mask ROM, an element of diode structure is used as a memory cell in place of an element of a MOS transistor structure.
FIG. 12 is a diagram showing a memory array structure of such an improved mask ROM disclosed in Japanese Patent Publication No. 61-1904. FIG. 12(a) is a plan view, and FIGS. 12(b) and (c) are sectional views taken along broken lines A and B, respectively, of the memory cell array of FIG. 12(a). Referring to FIG. 12, this memory cell array is formed on a semiconductor substrate 40 of monocrystal silicon. Substrate 40 has an insulation film (not shown) formed of silicon oxide film on the surface. A plurality of strips of N type polysilicon layers 42 are provided in parallel with each other on substrate 40. An insulation layer 41 is provided all over semiconductor substrate 40 and polysilicon layers 42. Insulation layer 41 is selectively provided with an opening, i.e. a contact hole 44. A P type polysilicon region 45 is formed by introducing impurities into polysilicon layer 42 under contact hole 44. A plurality of parallel strips of conductive layers 43 are provided on insulation layer 41 and contact hole 44 to cross polysilicon layer 42. Contact hole 44 is selectively provided at the crossing of polysilicon layer 42 and conductive layer 43. Each strip polysilicon layer 42 corresponds to a different word line. Each strip conductive layer 43 corresponds to a different bit line.
It can be seen from FIG. 12(a) that the crossings of a plurality of strip polysilicon layers 42 and a plurality of strip conductive layers 43 form a matrix. Referring to FIGS. 12(b) and (c), a PN junction is formed in polysilicon layer 42 beneath each contact hole 44. If forward voltage is applied to conductive layer 43 at the crossing having contact hole 44, current flows to polysilicon layer 42. The application of forward voltage to conductive layer 43 at the crossing not having contact hole 44 causes no current to flow to polysilicon layer 42 because conductive layer 43 is insulated from polysilicon layer 42 by insulation layer 41. By applying a predetermined voltage to a selected bit line and selecting a word line to detect the presence of current flowing thereof, determination can be made whether a contact hole is provided or not at the crossing of conductive layer 43 corresponding to the selected bit line and polysilicon layer 42 corresponding to the selected word line. It is therefore possible to conventionally read out stored information from a manufactured mask ROM by making the presence and absence of a contact hole correspond to logic values 1 and 0, and determine a formation pattern of contact holes according to the information to be stored in a mask ROM. Instead of the conventional usage of 1 MOS transistor as 1 memory cell, simply one PN junction, i.e. one diode is used. Therefore, the area necessary for one memory cell depends on the widths of conductive layer 43 and polysilicon layer 42.
The minimum values of the width of each conductive layer 43 and each polysilicon layer 42 are determined by the limit value of line-and-space in the current manufacturing techniques. By reducing these widths (within the range where a contact hole 44 can be formed), the area of one memory cell occupying the face of the substrate can be reduced significantly. Thus, a much smaller mask ROM can be obtained in comparison with the case where a MOS transistor is used as a memory cell.
The manufacturing steps of a mask ROM having a memory cell array of FIG. 12 will be explained with reference to FIGS. 13-15. FIGS. 13-15 are sectional views of a mask ROM showing an example of the manufacturing steps.
Referring to FIG. 13(a), N type impurities are selectively diffused onto the main surface of a P type substrate 111 having a low impurity concentration to form an island-like N well region 112. Then, an oxide film 113 is formed on the main surface of substrate 111 including N well region 112 (FIG. 13(b)). Oxide film 113 is thickly formed at the relative boundary portions of memory cell array region A, P channel MOS transistor region B forming the periphery of memory cell array region A, and N channel MOS transistor region C to serve as an oxide film for element isolation, and thinly in each regions of A, B and C so as not to degrade the transmittance of the impurities. Next, a conductive layer 114 corresponding to N type polysilicon layer 42 of FIG. 12 is formed on the main surface of substrate 111 corresponding to memory cell array region A. Conductive layer 114 is provided as a plurality of strip-like conductive layers vertical to the plane of the drawing sheet to form the word lines (FIG. 13(c)).
Then, a conductive layer of polysilicon layer 115 and metal layer 116 is formed on the main surface of substrate 111, as shown in FIG. 14(a), as the gate electrode and the interconnection layer in the respective P channel MOS transistor region B and N channel MOS transistor region C. Next, an oxide film 113 for insulation is again formed on the main surface of substrate 111. Referring to FIG. 14(b), an opening 201 is selectively provided in oxide film 113 and a resist 202 layered thereupon, in memory cell array region A. A P type polysilicon region 203 is formed by introducing P type impurities into polysilicon layer 114 at the bottom of opening 201. An N type region 117 forming the source and drain is formed in N channel MOS transistor region C by selectively diffusing N type impurities onto the main surface of substrate 111. A P type region 118 which is the source and drain of the P channel MOS transistor is formed by selectively diffusing P type impurities onto N well 112 (FIG. 14(c)). Then, an insulation film 119 is formed all over the main surface of substrate 111 to fill and make planar the entire surface of substrate 111. Referring to FIG. 14(d), a contact hole 120 is selectively formed in the insulation layer of insulation film 119 and oxide film 113. Contact hole 120 is formed to expose the surfaces of P type polysilicon region 203, N type region 117, and P type region 118 in memory cell array region A, N channel MOS transistor region C, and P channel MOS transistor region B, respectively.
Referring to FIG. 15, a conductive layer 121 of metal such as aluminum is selectively formed over insulation film 119 to fill contact hole 120. In memory cell array region A, a plurality of strips of conductive layers 121 are provided on insulation film 119 at right angles to each N-type polysilicon layer 114 forming a word line. Each of the plurality of conductive layers 121 corresponds to one bit line. In peripheral regions B and C, conductive layer 121 form an interconnection connected to the source/drain of a MOS transistor.
In a mask ROM manufactured in the above manner, positive voltage is applied only to conductive layer 114 forming a word line which corresponds to a MC required to have data read out, whereby the presence of current is sensed flowing through conductive layer 121 forming a bit line which corresponds to the memory cell MC. Determination is made whether the logic value of the stored data in the memory cell MC is 0 or 1 according to the sensed result. If there is a PN junction formed of P type region 117 and N type region 114 in the memory cell MC, the state of this PN junction becomes forward bias in response to the application of voltage to conductive layer 121 which is the bit line to cause current to flow to the corresponding conductive layer 114 forming a word line. Although the selected word line may comprise contact hole 120 in the crossing portion with other bit lines that are not selected, there is no possibility of the current in word line 114 to flow out to other bit lines that are not selected since the PN junction in each contact hole 120 attains a reverse-bias state. If there is no PN junction in memory cell MC, current will not flow to that memory cell MC since there is no contact hole 120 between that memory cell and the corresponding bit line.
At the locations corresponding to the crossings of a plurality of first strip conductive layers each forming one word line and a plurality of second strip conductive layers each forming one bit line provided at right angles to the first conductive layers in the above-described mask ROM advantageous to high integration density, a PN junction is selectively provided to electrically connect the first conductive layer and the second conductive layer. Each crossing functions as one memory cell. Although such a mask ROM is advantageous to high integration density since memory cells can be reduced in size, the manufacturing process thereof is not so simple since it is necessary to selectively form PN junctions. Many mask ROMs using a memory cell of a simple structure advantageous to high integration density which completely differ from mask ROMs which are currently available in the market include the above-described mask ROM having one memory cell formed by one PN junction.
Each of FIGS. 20 and 22A is a sectional views of a memory cell in a conventional mask ROM devised from the standpoint of increasing the number of data bits stored in a memory cell.
FIG. 20 shows a semiconductor memory device of a multi-value level method for storing a plurality of bits of information in each memory cell having a memory cell structure of a conventional mask ROM where one memory cell is formed by one MOS transistor.
Referring to FIG. 20, each memory cell comprises impurity diffusion layers 32a and 32b having a polarity opposite to that of a semiconductor substrate 31 and formed on semiconductor substrates 31 as a source and drain, and a gate electrode 33 extending over impurity diffusion layers 32a and 32b and formed above semiconductor substrate 31 with an insulation film 34 therebetween. Semiconductor substrate 31 is a P.sup.- type semiconductor substrate of low impurity concentration. Gate electrode 33 is formed of, for example, polysilicon and the like. Differing from the case of a conventional mask ROM storing one bit of data, impurities of a polarity identical to that of the impurities added to drain 32a and source 32b are added by ion implantation and the like at a concentration according to the data to be stored in that memory cell to the region between source 32b and drain 32a at the surface of semiconductor substrates 31, i.e. channel region 35 in each memory cell. The concentration of the impurities added to the channel region 35 of the memory cells forming one memory array is set to a plurality of values.
The threshold voltage of the MOS transistor increases in proportion to the gate voltage required to generate an inverted layer which has a polarity that is opposite to that of semiconductor substrate 31 on channel region 35. The electrical polarity of channel region 35 comes near to that of source 32b and drain 32a as the impurity concentration in channel region 35 rises. Therefore, an inverted layer is generated in channel region 35 even though the applied voltage of positive polarity (in the case where semiconductor substrate 31 is P type) or negative polarity (in the case where semiconductor substrate 31 is N type) towards gate electrode 33 is not so great. The electrical characteristic of a MOS transistor forming the memory cells included in one memory array can be set to a plurality of types by changing the impurity concentration applied to channel region 35 for each memory cell.
More specifically, if there are m types of impurity concentrations applied to channel region 35, the memory cells included in one memory array is divided into a first memory cell group having the lowest threshold voltage due to channel region 35 having the highest impurity concentration, a second memory cell group having a threshold voltage higher than that of the first memory cell group due to channel region 35 having an impurity concentration lower than that of the first memory cell group, . . . , and a m-th memory cell group having the highest threshold voltage due to channel region 35 having the lowest impurity concentration.
FIG. 21 is a graph showing the relationship between the gate potential and the current Ids across drain 32a and 32b of a MOS transistor having a threshold voltage of V.sub.TH1 (curve 41), a MOS transistor having a threshold voltage of V.sub.TH2 (curve 42) which is higher than threshold voltage V.sub.TH1, a MOS transistor having a threshold voltage of V.sub.TH3 (curve 43) which is further higher than threshold voltage V.sub.TH2, and a MOS transistor having a threshold voltage of V.sub.TH4 (curve 44) which is higher than threshold voltage V.sub.TH3. FIG. 21 shows the case where drain 32a and source 32b are 5 V and 0 V, respectively.
Referring to curves 41-44, a MOS transistor has a behavior according to an enhancement type as the impurity concentration of channel region 35 decreases, and a behavior according to a depletion type as the impurity concentration increases regarding its electrical characteristics. Therefore, if the same potential of V0b is set for the gate potential V.sub.G of the four types of MOS transistors, current Ids across drain 32a and source 32b shows the largest value of I1 in the MOS transistor having threshold voltage V.sub.TH1, a value of I2 which is smaller than I1 in the MOS transistor having threshold voltage V.sub.TH2, a value of I3 which is smaller than I2 in the MOS transistor having threshold voltage V.sub.TH3, and a value of 0 in the MOS transistor having threshold voltage V.sub.TH4. In other words, the current Ids across drain 32a and source 32b differs among the four types of MOS transistors. It is therefore possible to realize a mask ROM that has two bits of information previously stored in one memory cell by making the stored data of the four types of MOS transistors correspond to four different types of data according to currents of I1, I2, I3, and 0 when the gate potential V.sub.G, the drain 32a potential, and the source 32b potential are respectively V0b, 5V, and 0V.
By setting the potentials of drain 32asource 32b and gate 33 of the memory cell desired to have the stored data read out to 5 V, 0V, and V0b, respectively, and detecting the magnitude of current Ids across drain 32a and source 32b, the stored data of this memory cell is determined by the result corresponding to one of the above mentioned four different types of data.
Such a multi-value memory not using the memory cell structure of a conventional mask ROM is disclosed in Japanese Patent Laying-Open No. 58-122694.
FIG. 22A is a sectional view of a memory cell structure in a multi-value memory disclosed in Japanese Patent Laying-Open No. 58-122694. FIG. 23 is a graph showing the electrical characteristics of a memory cell having the structure shown in FIG. 22A.
FIG. 22B is a plan view of this memory cell array of multi-value memory. It can be appreciated from FIG. 22B that there are a plurality of strips of electrode conductors 51 crossing a plurality of strips of electrode conductors 53. Each crossing point 500 of the plurality of electrode conductors 51 and 53 is used as one memory cell. FIG. 22A shows the sectional view of a memory cell corresponding to one of crossing points 500.
Referring to FIG. 22A, each memory cell comprises an electrode conductor 51 formed of aluminum, an insulator 52 formed on electrode conductor 51, and an electrode conductor 53 formed of Pb on insulator 52. Insulator 52 is formed of Al.sub.2 O.sub.5. An additive substance 54 such as benzene and benzoic acid is added according to the stored data of the memory cell at the interface of insulator 52 and electrode conductor 53.
Referring to FIG. 23, the increase of voltage V applied between electrode conductors 51 and 53 to a level V.sub.T corresponding to an energy of exciting mode particular to additive substance 54 causes a sudden increase of current I flowing between electrode conductors 51 and 53 due to inelastic tunnel effect. Voltage V.sub.T is, for example, 0.36 V when additive substance 54 is benzene, and 0.4 V when benzoic acid. The sudden increasing level V.sub.T of current I between electrode conductors 51 and 53 differs according to the type of substance 54 added to the interface of insulator 52 and electrode conductor 53. If an additive substance 54 is not added to the interface of insulator 52 and electrode conductor 53, such a non-elastic tunnel effect does not occur so that current I will not suddenly increase even if the applied voltage to electrode conductors 51 and 53 is raised.
Therefore, by detecting the increasing rate dI/dV of current I across electrode conductors 51 and 53 to applied voltage V between electrode conductors 51 and 53, the existence and the type of the additive substance between insulator 52 and electrode conductor 53 of the memory cell can be identified according to the presence of sudden increasing point V.sub.T of current I and the magnitude of voltage V at this sudden increasing point V.sub.T. A plurality of bit data can be stored in one memory cell by establishing two or more types of substances used as additive substance 54.
For example, if two types of additive substance 54 of benzene and benzoic acid are used, one memory cell array comprises three types of memory cells of: (1) a memory cell not having additive substance 54 added, (2) a memory cell having benzene added as additive substance 54, and (3) a memory cell having benzoic acid added as additive substance 54. The stored data of these three types of memory cells can be made to correspond to three types of data according to the presence/absence and type additive substance 54 in the interface of insulator 52 and electrode conductor 53. By detecting the increasing rate dI/dV in each memory cell, the stored data of each memory cell can be identified which of the three types of data it represents according to the presence of sudden increasing point V.sub.T of current I and voltage V between electrode conductors 51 and 53 at the sudden increasing point V.sub.T. Because the application of two or more types of substances as additive substance 54 to the interface of insulator 52 and electrode conductor 53 of FIG. 22A results in two or more points of sudden increase in current across electrode conductors 51 and 53, two or more bits of information can be stored at the location corresponding to each of the interconnections of electrode conductors 51 and 53 to implement a multi-value memory.
Such a conventional multi-value memory is realized by using the advantages that the magnitude of current across the drain and source of a MOS transistor is variable by the impurity concentration at the channel region, and that the increasing point due to non-elastic tunnel effect of current flowing across two conductors sandwiching an insulator is variable according to the types of substances added to the interface of the insulator and one of the two conductors. Such a conventional multi-value memory has problems which will be described hereinafter.
The structure of each memory cell takes a field effect transistor type such as that shown in FIG. 20 when a plurality of bits of data are stored in one memory cell by setting in stages impurity concentrations in the channel region. Each memory cell requires regions corresponding to the gate, the drain, and the source on a semiconductor substrate. Therefore, although the amount of information that can be stored in each memory can be increased, there is a limit in increasing the integration density of a memory device since the number of memory cells formed on one chip cannot be reduced considerably. There is also a disadvantage that the step of ion implantation towards channel region 35 is complicated because it is necessary to provide more than two different impurity concentrations for channel region 35 in the memory cells on one chip.
The multi-value memory (refer to FIG. 22) utilizing non-elastic tunnel effect has the area necessary for each memory cell dependent on the width of conductors 51 and 53, since each intersection 500 of strips of conductors 51 and 53 sandwiching insulator 52 is used as one memory cell. By reducing the width of conductors 51 and 53, the occupying area of each memory cell can be significantly reduced than that in the case where a MOS transistor is used as each memory cell. Therefore, such a multi-value memory is superior than the above-described multi-value memory from the standpoint of increase in integration density of a memory device. However, a plurality of types of memory cells having different types of additive substances 54 added to the interface of insulator 52 and conductor 53, and one not having additive substance 54 added, must be provided. This means that additive substance 54 must be selectively added to the interface of insulator 52 and conductor 53. The number of types of substances added to the interface of insulator 52 and conductor 53 must be increased in proportion to the number of bits of information stored in one memory cell, so that the manufacturing step of adding additive substance 54 to the interface becomes complicated.